The present invention relates generally to virtual prototyping. Specifically, the invention relates to a method for predictive simulation and power estimation of microdevices and microsystems.
Portable and high-density micro-electronic devices make power dissipation of very large scale integrated (VLSI) circuits a critical concern. Because of limited battery life, reliability issues, and packaging and cooling costs, power consumption for devices is a critical design concern. To avoid issues associated with excessive power consumption, computer design helps to estimate power consumption of VLSI designs.
The rapid progress in microsystems technology is increasingly supported by specific modeling methods and dedicated simulation tools. These methods not only enable the visualization of fabrication processes and operational principles, but also assist a designer to make decisions for finding optimized microstructures under relevant technological and economical constraints. Currently efforts are being made towards using simulation platforms for the predictive simulation of microsystems, i.e., the “virtual fabrication” and “virtual experimentation and characterization” on a computer.
A digital semiconductor chip is often designed using a Hardware Description Language (HDL) such as Verilog or VHDL (Very High-Speed Integrated Circuit, VHSIC, Hardware Description Language). To verify that the design operates according to the design specification, it must be simulated in a verification environment. These simulations are typically done using commonly available simulation tools such as NC Sim (from Cadence) and VCS (from Synopsys). Other simulators from various different vendors may also be used. As these simulations run in a “cycle-accurate” mode, they tend to be very accurate in representing the behavior of the design. In “cycle accurate mode,” the real clock signal that is expected to be provided to the semiconductor chip is supplied to the design during simulations. Since the real clock signal cycles many times during simulations, the simulations tend to be very slow, as each clock cycle (or “tick”) necessitates evaluation of the simulator events. Typically, modern digital design involves clock signal frequencies of several million cycles per second to several billion cycles per second. Thus, simulating real world conditions which happen over several minutes becomes extremely slow.
One of the methods to speed up these simulations and increase the simulation performance is to represent the semiconductor design in a higher abstraction level. The higher abstraction representation of the semiconductor design will use the concept of Transaction Level Modeling (or TLM) to model the behavior of the semiconductor design. Such a higher abstraction model might be written with a language like SystemC, SystemVerilog, C, C++ or any other suitable language. This higher abstraction model is known as a “Virtual Prototype” of the semiconductor design. The virtual prototype can then be simulated in a SystemC simulator (many simulation tools are available from various vendors). The simulations in a SystemC/TLM simulator tend to be much faster, up to 200 or 300 times faster as compared to the semiconductor design simulations.
The acceleration is due to the simulations run in one of the following modes prescribed by the standards committee for SystemC/TLM modeling, Accelera.                A) “untimed”—where no clock signal used.        B) “approximately timed”—different transaction “phases” are used to time the model (clock signal is used rarely in this mode).        C) “loosely timed”—more transaction phases are used than in B (clock signal is used occasionally in this mode).        
In A, the clock signal is not used at all. In B, the clock signal is rarely used; instead the model relies on the “start” phase of a transaction or event occurring within the block and the “end phase” of that transaction or event. In C, more phases of the transaction are used to time the model (start phase, active phase, acknowledgement phase, end phase, etc. More phases may be defined by the user as required).
There is no “cycle accurate” mode prescribed by Accelera when building and simulating a virtual prototype. Cycle accurate mode is the most accurate mode used to simulate the real semiconductor design using the real clock signal, as described previously. Accelera usually recommends that the number of modes be no greater than three. The present invention may comprise a number of modes greater than three.
The challenge: In a semiconductor design built using an HDL (like Verilog or VHDL) it is easier to estimate the power consumption based on the frequency of the clock signal that the design runs on, and several other parameters inside the design. This results in a fairly accurate estimation of the power that the design might consume, once it is applied into a real world semiconductor chip. However, in a virtual prototype of the semiconductor design, any power estimation will not be accurate. The reason is that semiconductor design simulations always run in a “cycle-accurate” mode, using every clock tick of the real clock signal. In the virtual prototype, in the any of the timing modes: untimed, approximately timed or the loosely timed, the clock used is an approximation of the real clock signal.
Power estimation can be hampered in complexity, time, and cost, by engaging in model synthesis. Power estimation without performing the model synthesis step, has been avoided due to the industry's failure to develop a method of estimating power that excludes model synthesis. If the power estimation process could be performed without model synthesis, then time and costs could be decreased.
There is a need to give an accurate estimation of the power consumed in a virtual prototype, because today's low-power semiconductor designs demand an estimation of power from the virtual prototyping systems. The virtual prototype is typically built very early on in the design process. Thus, if the prototype could provide an accurate estimation of power, it helps the user to make better design choices, before the design gets finalized. Also, the method should look towards streamlining where feasible, such as concerning synthesis steps.